One process frequently employed during fabrication of semiconductor devices is formation of an etched cylinder or other recessed feature in a stack of dielectric-containing material. For instance, such processes are commonly used in memory applications such as fabricating 3D NAND (also referred to as vertical NAND or V-NAND) structures. As the semiconductor industry advances and device dimensions become smaller, such features are increasingly difficult to etch in a uniform manner, especially for high aspect ratio cylinders having narrow widths and/or deep depths.
The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.